---------------------------------------------------------------------------------- -- Engineer: Benjamin Yee amd Hasham Ali -- -- Create Date: 11/29/2015 07:15:11 PM -- Design Name: -- Module Name: Source - Behavioral -- Project Name: Tally Counter -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity FSM2 is Port ( clk : in STD_LOGIC; Clear : in STD_LOGIC; Initial : in STD_LOGIC_VECTOR (7 downto 0) := "00000000"; Final : out STD_LOGIC_VECTOR (7 downto 0); Binary_state : out STD_LOGIC_vector(1 downto 0); En : in STD_LOGIC); end FSM2; architecture Behavioral of FSM2 is type state is (ST0, ST1, ST2, ST3); signal PS,NS : state; signal Omega : std_logic_vector (7 downto 0); signal Dmega : std_logic_vector (7 downto 0); begin Clear_process: process (clk,NS,Clear) --clear button process begin if (Clear = '1') then PS <= ST3; elsif (rising_edge(clk)) then PS <= NS; end if; end process Clear_process; Omega <= Initial; Dmega <= Initial; Enable_Process: process (PS,Initial,Omega,clk,Dmega, En) begin case PS is when ST0 => --Initial state if (En = '0') then NS <= ST1; --When the program starts up, go to ST1 else NS <= ST0; end if; when ST1 => -- when this FSM2 receives FSM1 enable signal if (En = '1') then NS <= ST2; else NS <= ST1; end if; when ST2 => if(rising_edge(clk)) then Omega <= Omega + 1; -- on the rising edge, increment the bit by one end if; if (Dmega = Omega) then NS <= ST0; else NS <= ST2; end if; when ST3 => Omega <= "00000000"; NS <= ST0; when others => -- if the value goes over "11111111" goes back to 0 NS <= ST0; Omega <= "00000000"; end case; Final <= Omega; end process Enable_Process; Final <= Omega; with PS select Binary_state <= "01" when ST0, -- LED encoding "10" when ST1, "11" when ST2, "00" when others; end Behavioral;