---------------------------------------------------------------------------------- -- Company: Cal Poly CPE 133 -- Engineer: Lauren Byrne and Christopher Gerdom -- -- Create Date: 16:01:44 11/23/2014 -- Design Name: -- Module Name: game_mem_driver - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity game_mem_driver iS Port ( LOGIC_ADDR : in STD_LOGIC_VECTOR (15 downto 0); DISP_ADDR : in STD_LOGIC_VECTOR (15 downto 0); DATA_IN : in STD_LOGIC_VECTOR (2 downto 0); DISPLAY_PRIORITY : in STD_LOGIC; MEM_CLK : in STD_LOGIC; RESET : in STD_LOGIC; WRITE_EN: in STD_LOGIC; --MEMORY OUTPUTS DATA_OUT : out STD_LOGIC_VECTOR (2 downto 0):="000"; WRITEN : out STD_LOGIC:='0'); end game_mem_driver; architecture Behavioral of game_mem_driver is COMPONENT GameMem IS PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(2 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END COMPONENT; component adress_sel is Port ( DISP_ADDR : in STD_LOGIC_VECTOR (15 downto 0); LOGIC_ADDR : in STD_LOGIC_VECTOR (15 downto 0); WRITE_EN : in STD_LOGIC; DISPLAY_PRIORITY : in STD_LOGIC; SELECTED_ADDR : out STD_LOGIC_VECTOR (15 downto 0); WRITE_CONT : out STD_LOGIC); end component; signal selected_addr : STD_LOGIC_VECTOR(15 downto 0); signal data_hold : STD_LOGIC_VECTOR(2 downto 0):="000"; signal write_cont : STD_LOGIC; begin MEM0: gameMem port map ( clka=>MEM_CLK, rsta=>RESET, wea(0)=> write_cont, addra=>selected_addr, dina=>DATA_IN, douta=>data_out ); addr_sel0: adress_sel port map ( DISP_ADDR => DISP_ADDR, LOGIC_ADDR => LOGIC_ADDR, WRITE_EN => WRITE_EN, DISPLAY_PRIORITY => DISPLAY_PRIORITY, SELECTED_ADDR =>SELECTED_ADDR, WRITE_CONT =>WRITE_CONT ); writen<= write_cont; end Behavioral;