------------------------------------------------------------------ -- Engineer: Andrew Danowitz -- Creation Date: 10/04/2016 -- Description: Template for test benches. Note, this is a recreation -- of Dr. Benson's template seen in the video here -- https://www.youtube.com/watch?v=B-QluddPojI ------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; --make the entity name of your simulation file the same name as the file you --wish to simulate with the word Sim at the end of it. The entity is empty --because a simulation file can not be turned into logic or put on a board. entity simulation is end simulation; architecture Behavioral of simulation is --Component Declaration for the Unit Under Test (UUT), sometimes known as --the Design Under Test (DUT). This is the entity you wish to simulate. component EnergySavingLight is Port ( clk : in STD_LOGIC; switch : in STD_LOGIC; sensor : in STD_LOGIC_VECTOR (1 downto 0); LEDs : out STD_LOGIC_VECTOR (2 downto 0)); end component; --Signal declarations - these will connect to your UUT's ports. Can be the --same name as your UUT ports signal sensor : std_logic_vector(1 downto 0); signal switch : std_logic := '0'; signal LEDs : std_logic_vector(2 downto 0); --For designs with a clock (CLK), uncomment the following signal CLK : std_logic := '0'; constant CLK_period: time := 10 ns; begin --Map the UUT's ports to the signals uut: EnergySavingLight port map ( sensor => sensor, clk => clk, switch => switch, LEDs => LEDs ); --For designs with a CLK uncomment the following. Note that this is slightly --different than the process in Dr. Benson's video, but should work just --the same. Why is that? CLK_process : process begin wait for CLK_period/2; CLK <= not CLK; end process; --this is where we test our circuit. Note that this is a pretty basic form --of testbench, you manually provide a stimulus and have to visually confirm --that the output is correct on a testbench waveform. For larger designs, --you might wish to procedurally generate stimulus using a loop, or read --stimulus in from a file. You would also wish to use assertions so that --the simulator tests each set of input conditions against an expected --output and tells you when an error is detected. stim_proc: process begin switch <= '1'; sensor <= "00"; wait for 30 ns; switch <= '1'; sensor <= "01"; wait for 30 ns; switch <= '1'; sensor <= "10"; wait for 30 ns; switch <= '1'; sensor <= "11"; wait for 60 ns; switch <= '1'; sensor <= "00"; wait for 120 ns; switch <= '0'; sensor <= "11"; wait; end process; end Behavioral;