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-- Company: 
-- Engineer: 
-- 
-- Create Date: 11/12/2016 07:10:15 PM
-- Design Name: 
-- Module Name: flipflop_jk - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity flipflop_jk is
    Port ( J : in STD_LOGIC;
           K : in STD_LOGIC;
           EI : in STD_LOGIC;
           clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           Q : out STD_LOGIC);
    signal Q_feedback, J_sig : STD_LOGIC;
end flipflop_jk;


architecture Behavioral of flipflop_jk is


begin

    Q <= Q_feedback;
    J_sig <= J and EI;
    process (rst, clk) is
    begin
        if (rising_edge(clk)) then
        Q_feedback <= (J_sig AND NOT Q_feedback) OR (NOT K AND Q_feedback);
        end if;
        if (rst = '1') then
            Q_feedback <= '0';
        end if;
    end process;
        





end Behavioral;