---------------------------------------------------------------------------------- -- Company: Cal Poly EE Department -- Engineer: Riley Olson, Dan Potts, Bill Blakely -- -- Create Date: 12/02/2015 08:02:16 PM -- Design Name: -- Module Name: REF - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: This module takes inputs DECR_X and RS_X from the CONTROL module and generates a a 7-bit X_REF signal which can then be used to generate a PWM signal -- -- Dependencies: None -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- entity REF is Port ( CLK : in STD_LOGIC; DECR_X : in STD_LOGIC; RS_X : in STD_LOGIC; X_REF : out STD_LOGIC_VECTOR(6 downto 0)); end REF; architecture Behavioral of REF is begin process(CLK, DECR_X, RS_X) variable X_VAL : integer := 127; begin if(rising_edge(CLK)) then if(DECR_X = '1') then X_VAL := X_VAL - 1;--decrements the reference signal elsif(RS_X = '1') then X_VAL := 127;--resets the reference signal end if; if(X_VAL < 0) then X_VAL := 127;--ensures X_VAL isn't negative end if; X_REF <= STD_LOGIC_VECTOR(to_unsigned(X_VAL, 7));--converts the integer value X_VAL to a 7-bit signal end if; end process; end Behavioral;