---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:34:20 11/23/2014 -- Design Name: -- Module Name: counter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( start_counter : in STD_LOGIC; clk : in STD_LOGIC; Reset : in STD_LOGIC; counter_max : out STD_LOGIC); end counter; architecture Behavioral of counter is signal counter : integer range 0 to 50000000 := 0; begin frequency_divider: process (start_counter, reset, clk) begin if (reset = '1') then counter <= 0; elsif rising_edge(clk) then counter_max <= '0'; if ( counter = 0 and start_counter = '1') then counter <= 1; elsif counter = 50000000 then counter <= 0; counter_max <= '1'; elsif counter > 0 then counter <= counter + 1; end if; end if; end process; end Behavioral;