---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05/30/2018 12:50:15 PM -- Design Name: -- Module Name: octave - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity octave is Port ( btnc : in STD_LOGIC; clk : in std_logic; oct : out std_logic_vector(1 downto 0)); end octave; architecture Behavioral of octave is type state_type is (A,B,C,D); signal state : state_type := A; signal sclk : std_logic; component clk_div_octave port (clk : in std_logic; sclk : out std_logic); end component; begin o_clk_div: clk_div_octave port map(clk => clk, sclk => sclk); process(sclk, btnc) begin if rising_edge(sclk) and btnc = '1' then case state is when A => oct <= "00"; state <= B; when B => oct <= "01"; state <= C; when C => oct <= "10"; state <= D; when D => oct <= "11"; state <= A; end case; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ----------------------------------------------------------------------- -- Module to divide the clock ----------------------------------------------------------------------- entity clk_div_octave is Port ( clk : in std_logic; sclk : out std_logic); end clk_div_octave; architecture my_clk_div of clk_div_octave is constant max_count : integer := (25000000); signal tmp_clk : std_logic := '0'; begin my_div: process (clk,tmp_clk) variable div_cnt : integer := 0; begin if (rising_edge(clk)) then if (div_cnt = MAX_COUNT) then tmp_clk <= not tmp_clk; div_cnt := 0; else div_cnt := div_cnt + 1; end if; end if; sclk <= tmp_clk; end process my_div; end my_clk_div;