---------------------------------------------------------------------------------- -- Company: Cal Poly San Luis Obispo -- Engineer: Chase Timmins / Shivani Ganti -- -- Create Date: 11/29/2017 11:23:53 AM -- Design Name: -- Module Name: Pong_Master - Behavioral -- Project Name: Pong_Game -- Description: Master file for final project -- -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Adjusted frequency for VGA Module -- Revision 0.03 - Added Debouncer for Start Button -- Revision 0.04 - Added Debouncer for Timer signal -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Pong_Master is Port ( Bttn_L : in STD_LOGIC; Bttn_R : in STD_LOGIC; Bttn_S : in STD_LOGIC; Bttn_RST : in STD_LOGIC; Clk : in STD_LOGIC; HS : out STD_LOGIC; VS : out STD_LOGIC; An : out STD_LOGIC_VECTOR (3 DOWNTO 0); Seg : out STD_LOGIC_VECTOR (6 DOWNTO 0); Rout : out STD_LOGIC_VECTOR (2 DOWNTO 0); Gout : out STD_LOGIC_VECTOR (2 DOWNTO 0); Bout : out STD_LOGIC_VECTOR (1 DOWNTO 0)); end Pong_Master; architecture Behavioral of Pong_Master is -- Components component Score_Handler is Port ( PS : in STD_LOGIC_VECTOR (2 downto 0); Clk : in STD_LOGIC; RST : in STD_LOGIC; An : out STD_LOGIC_VECTOR (3 downto 0); Seg : out STD_LOGIC_VECTOR (6 downto 0)); end component; component Clk_Div is Port ( Clk : in STD_LOGIC; CEN : in STD_LOGIC; Div : in STD_LOGIC_VECTOR (27 downto 0); Clk_Out : out STD_LOGIC); end component; component vgaDriverBuffer is Port ( CLK, we : in std_logic; wa : in std_logic_vector (10 downto 0); wd : in std_logic_vector (7 downto 0); Rout : out std_logic_vector(2 downto 0); Gout : out std_logic_vector(2 downto 0); Bout : out std_logic_vector(1 downto 0); HS : out std_logic; VS : out std_logic; pixelData : out std_logic_vector(7 downto 0) ); end component; component Flow_FSM is Port ( Clk : in STD_LOGIC; -- Clk: Refresh rate of the FMS Fail : in STD_LOGIC; -- Fail: Input from the image processor determining if the game should end Timer : in STD_LOGIC; -- Timer: Input from the timer telling if the FSM needs to advance to the next level Bttn_S : in STD_LOGIC; -- Bttn_S: Start button input Bttn_RST : in STD_LOGIC; -- Bttn_RST: Reset button input Pres_S : out STD_LOGIC_VECTOR (2 downto 0)); -- Pres_S: Present State output to other devices end component; component IMG_Process is Port ( Bttn_L : in STD_LOGIC; Bttn_R : in STD_LOGIC; -- Bttn_S : in STD_LOGIC; Bttn_RST : in STD_LOGIC; Clk : in STD_LOGIC; PS : in STD_LOGIC_VECTOR (2 downto 0); B_X : out STD_LOGIC_VECTOR (5 downto 0); B_Y : out STD_LOGIC_VECTOR (4 downto 0); P_X1 : out STD_LOGIC_VECTOR (5 downto 0); P_X2 : out STD_LOGIC_VECTOR (5 downto 0); Fail : out STD_LOGIC); end component; component Refresh_IMG is Port ( Clk : in STD_LOGIC; -- Refresh rate of the VGA P_X1 : in STD_LOGIC_VECTOR (5 downto 0); -- Left-most edge (x-coordinate) of the paddle P_X2 : in STD_LOGIC_VECTOR (5 downto 0); -- Right-most edge (x-coordinate) of the paddle B_X : in STD_LOGIC_VECTOR (5 downto 0); -- X-coordinate of the Ball B_Y : in STD_LOGIC_VECTOR (4 downto 0); -- Y-coordinate of the Ball PS : in STD_LOGIC_VECTOR (2 downto 0); -- Present State of the Game FSM RST : in STD_LOGIC; -- Reset signal WE : out STD_LOGIC; -- Write enable WD : out STD_LOGIC_VECTOR (7 downto 0); -- Write Data WA : out STD_LOGIC_VECTOR (10 downto 0));-- Write Address end component; component Timer_Div is Port ( Clk : in STD_LOGIC; PS : in STD_LOGIC_VECTOR (2 downto 0); Timer : out STD_LOGIC; Clk_out : out STD_LOGIC); end component; component Start_Debounce is Port ( S_in : in STD_LOGIC; Clk : in STD_LOGIC; S_out : out STD_LOGIC); end component; -- Signals signal Fail, -- Signal that indicates if Game Over or not to FSM Timer, -- Timer signal that indicates if it's time to move to the next level for FMS db_Timer, -- Debounced Timer STRT, -- Debounced Start signal WE, -- Enable writing to VGA Clk_timer, -- Clock signal from state_timer to animation_brain Clk_mod, -- Clock signal going to the VGA module Clk_VGA : std_logic := '0'; -- Clock signal from VGA_Clk.Clk_Out to refresher, refresh rate of the VGA signal W_D : std_logic_vector (7 downto 0); -- Color data being written signal W_A : std_logic_vector (10 downto 0); -- Address color data is being written to on the VGA signal P_X1, -- Left position of the Paddle P_X2, -- Right position of the paddle B_X : std_logic_vector (5 downto 0); -- X-position of the ball signal B_Y : std_logic_vector (4 downto 0); -- Y-position of the ball signal PS : std_logic_vector (2 downto 0); -- Present state of the FSM signal pix : std_logic_vector (7 downto 0); -- Storage for the pixel data, The VGA Driver I used had an extra output that had to be stored somewhere begin -- Instantiating all of the components VGA_clk: Clk_Div port map (Clk => Clk, CEN => '1', Div => X"00003E8", Clk_Out => Clk_VGA); VGA_mod_clk: Clk_Div port map (Clk => Clk, CEN => '1', Div => X"0000001", Clk_Out => Clk_mod); -- Start Debounce d_bounce: Start_Debounce port map (S_in => Bttn_S, Clk => Clk, S_out => STRT); -- Debounce but this time for the timer signal timer_d_bounce: Start_Debounce port map (S_in => Timer, Clk => Clk, S_out => db_Timer); state_machine: Flow_FSM port map (Clk => Clk, Fail => Fail, Timer => db_Timer, Bttn_S => STRT, Bttn_RST => Bttn_RST, Pres_S => PS); score: Score_Handler port map (Clk => Clk, PS => PS, RST => Bttn_RST, An => An, Seg => Seg); state_timer: Timer_Div port map (Clk => Clk, PS => PS, Timer => Timer, Clk_out => Clk_timer); refresher: Refresh_IMG port map (Clk => Clk_VGA, P_X1 => P_X1, P_X2 => P_X2, B_X => B_X, B_Y => B_Y, PS => PS, RST => Bttn_RST, WE => WE, WD => W_D, WA => W_A); animation_brain: IMG_Process port map (Clk => Clk_timer, Bttn_L => Bttn_L, Bttn_R => Bttn_R, Bttn_RST => Bttn_RST, PS => PS, B_X => B_X, B_Y => B_Y, P_X1 => P_X1, P_X2 => P_X2, Fail => Fail); drive_buffer: vgaDriverBuffer port map (Clk => Clk_mod, we => WE, wa => W_A, wd => W_D, Rout => Rout, Gout => Gout, Bout => Bout, HS => HS, VS => VS, pixelData => pix); end Behavioral;