---------------------------------------------------------------------------------- -- Company: Cal Poly CPE 133 -- Engineer: Lauren Byrne and Christopher Gerdom -- -- Create Date: 11:17:24 11/24/2014 -- Design Name: -- Module Name: vga_encoder - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity vga_encoder is Port ( X : in STD_LOGIC_VECTOR (10 downto 0); Y : in STD_LOGIC_VECTOR (10 downto 0); DATA : in STD_LOGIC_VECTOR (2 downto 0); -- RESET: IN STD_LOGIC; BLANKING: IN STD_LOGIC; PRIORITY : out STD_LOGIC; ADDRESS_OUT : out STD_LOGIC_VECTOR (15 downto 0); R : out STD_LOGIC_VECTOR (2 downto 0); G : out STD_LOGIC_VECTOR (2 downto 0); B : out STD_LOGIC_VECTOR (1 downto 0)); end vga_encoder; architecture Behavioral of vga_encoder is component x_y_mem_address is Port ( X : in STD_LOGIC_VECTOR (10 downto 0); Y : in STD_LOGIC_VECTOR (10 downto 0); ADDRESS_OUT : out STD_LOGIC_VECTOR (15 downto 0)); end component; begin addr_gen0: x_y_mem_address port map ( X=> X, y=>Y, ADDRESS_OUT=> ADDRESS_OUT ); priority<= not(blanking); VGA_ENC0: PROCESS (BLANKING,DATA) BEGIN IF (BLANKING='1') THEN R<="000"; G<="000"; B<="00"; ELSE R<=DATA(2)&DATA(2)&DATA(2); G<=DATA(1)&DATA(1)&DATA(1); B<=DATA(0)&DATA(0); END IF; END PROCESS VGA_ENC0; end Behavioral;