---------------------------------------------------------------------------------- -- Company: Cal Poly San Luis Obispo -- Engineer: Chase Timmins / Shivani Ganti -- -- Create Date: 11/20/2017 05:40:12 PM -- Design Name: -- Module Name: Refresh_IMG - Behavioral -- Project Name: Pong_Game -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 - Added input signal Clk -- Revision 0.03 - Added RST input signal -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Refresh_IMG is Port ( Clk : in STD_LOGIC; -- Refresh rate of the VGA P_X1 : in STD_LOGIC_VECTOR (5 downto 0); -- Left-most edge (x-coordinate) of the paddle P_X2 : in STD_LOGIC_VECTOR (5 downto 0); -- Right-most edge (x-coordinate) of the paddle B_X : in STD_LOGIC_VECTOR (5 downto 0); -- X-coordinate of the Ball B_Y : in STD_LOGIC_VECTOR (4 downto 0); -- Y-coordinate of the Ball PS : in STD_LOGIC_VECTOR (2 downto 0); -- Present State of the Game FSM RST : in STD_LOGIC; -- Reset signal WE : out STD_LOGIC; -- Write enable WD : out STD_LOGIC_VECTOR (7 downto 0); -- Write Data WA : out STD_LOGIC_VECTOR (10 downto 0));-- Write Address end Refresh_IMG; architecture Behavioral of Refresh_IMG is -- Components component Play_Counter is Port ( Clk : in STD_LOGIC; CEN : in STD_LOGIC; RST : in STD_LOGIC; B_X : in STD_LOGIC_VECTOR (5 DOWNTO 0); B_Y : in STD_LOGIC_VECTOR (4 DOWNTO 0); P_L : in STD_LOGIC_VECTOR (5 DOWNTO 0); P_R : in STD_LOGIC_VECTOR (5 DOWNTO 0); WA : out STD_LOGIC_VECTOR (10 DOWNTO 0); WD : out STD_LOGIC_VECTOR (7 DOWNTO 0)); end component; component Start_Counter is Port (Clk : in STD_LOGIC; CEN : in STD_LOGIC; RST : in STD_LOGIC; WA : out STD_LOGIC_VECTOR (10 DOWNTO 0); WD : out STD_LOGIC_VECTOR (7 DOWNTO 0)); end component; component Fail_Counter is Port ( Clk : in STD_LOGIC; CEN : in STD_LOGIC; RST : in STD_LOGIC; WA : out STD_LOGIC_VECTOR (10 downto 0); WD : out STD_LOGIC_VECTOR (7 downto 0)); end component; -- Signals signal Screen_Start, Screen_GO, Screen_Play : STD_LOGIC := '0'; signal WA_P, WA_S, WA_F : STD_LOGIC_VECTOR (10 DOWNTO 0); signal WD_P, WD_S, WD_F : STD_LOGIC_VECTOR (7 DOWNTO 0); begin -- Instantiated Components play: Play_Counter port map (Clk => Clk, CEN => Screen_Play, RST => RST, B_X => B_X, B_Y => B_Y, P_L => P_X1, P_R => P_X2, WA => WA_P, WD => WD_P); start: Start_Counter port map (Clk => Clk, CEN => Screen_Start, RST => RST, WA => WA_S, WD => WD_S); fail: Fail_Counter port map (Clk => Clk, CEN => Screen_GO, RST => RST, WA => WA_F, WD => WD_F); WE <= Screen_Start or Screen_GO or Screen_Play; -- State Logic: Turns on the corresponding signals for the display. state_logic: process (PS) begin case (PS) is when "000" => Screen_Start <= '1'; Screen_GO <= '0'; Screen_Play <= '0'; when "110" => Screen_Start <= '0'; Screen_GO <= '1'; Screen_Play <= '0'; when others => Screen_Start <= '0'; Screen_GO <= '0'; Screen_Play <= '1'; end case; end process; -- State Output: Determines which output counter to display based on the state_output: process (PS) begin case (PS) is when "000" => WA <= WA_S; WD <= WD_S; when "110" => WA <= WA_F; WD <= WD_F; when others => WA <= WA_P; WD <= WD_P; end case; end process; end Behavioral;