---------------------------------------------------------------------------------- -- Company: CPE 133 Digital Design -- Engineer: Michael Djaja, Ian Brown, Christian Cooper, William Le -- -- Create Date: 11/18/2015 10:29:45 AM -- Design Name: -- Module Name: Count - Behavioral -- Project Name: SmartSwitch Light Switch -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Count is Port ( Clk : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR(2 downto 0); Count_out : out STD_LOGIC_VECTOR(8 downto 0)); end Count; architecture Behavioral of Count is signal count_reg: UNSIGNED(8 downto 0); signal count_next: UNSIGNED(8 downto 0); begin process( Clk) begin if (rising_edge(clk)) then count_reg <= count_next; end if; end process; count_next <= count_reg + 1 when Sel="000" else --output of FSM count_reg - 1 when Sel="001" else "000000001" when Sel = "010" else (others => '0') when Sel = "011" else count_reg; Count_out <= STD_LOGIC_VECTOR(count_reg); end Behavioral;