---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:30:43 12/02/2014 -- Design Name: -- Module Name: MUX - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity MUX is Port ( Q : in STD_LOGIC_VECTOR(3 downto 0); SEL : in STD_LOGIC; MUX_VAL : out STD_LOGIC_VECTOR(3 downto 0)); end MUX; architecture Behavioral of MUX is begin MUX: process ( Q, SEL) begin if ( Sel = '1' ) then MUX_VAL <= Q; else MUX_VAL <= "0000"; end if; end process; end Behavioral;