---------------------------------------------------------------------------------- -- Company: -- Engineer: Chris Harlow, Dalton Wunderlich, Ryan Ortiz, Ramone Crespo -- -- Create Date: 11/20/2015 09:35:34 AM -- Design Name: -- Module Name: register - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Reg is generic (N: integer := 4); port ( Din: in std_logic_vector(N-1 downto 0); Dout: out std_logic_vector(N-1 downto 0); CLK: in std_logic; load: in std_logic; shift: in std_logic; clear: in std_logic; input: in std_logic); end Reg; architecture Behavioral of Reg is signal Dint: std_logic_vector(N-1 downto 0); begin process (CLK) begin if (rising_edge(CLK)) then if (clear = '1') then Dint <= (others => '0'); elsif (load = '1') then Dint <= Din; elsif (shift = '1') then Dint <= input & Dint(N-1 downto 1); end if; end if; end process; Dout <= Dint; end Behavioral;