---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 02/13/2018 01:50:29 PM -- Design Name: -- Module Name: dff - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dff is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC; en : in STD_LOGIC); end dff; architecture Behavioral of dff is begin process (clk, en) begin if en = '1' then if rising_edge(clk) then q <= d; end if; end if; end process; end Behavioral;