---------------------------------------------------------------------------------- -- Company: CPE 133 -- Engineer: William Le, Ian Brown, Christian Cooper, Michael Djaja -- -- Create Date: 12/03/2015 04:03:08 PM -- Design Name: -- Module Name: Final_Final - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Final_Final is Port ( Leds : out STD_LOGIC_VECTOR(1 downto 0); Rxs : in STD_LOGIC_VECTOR(1 downto 0); Clk : in STD_LOGIC; Reset : in STD_LOGIC; Auto : in STD_LOGIC; Set : in STD_LOGIC; O_light : out STD_LOGIC; I_light : out STD_LOGIC; Light : out STD_LOGIC; Count_out : out STD_LOGIC_VECTOR(8 downto 0)); end Final_Final; architecture Behavioral of Final_Final is component Full_system is Port ( O : in STD_LOGIC; I : in STD_LOGIC; Clk : in STD_LOGIC; Reset : in STD_LOGIC; Auto : in STD_LOGIC; Set : in STD_LOGIC; Light : out STD_LOGIC; Count_Output : out STD_LOGIC_VECTOR(8 downto 0)); end component Full_system; component IR_Beam_Split is Port ( LED : out STD_LOGIC; RX : in STD_LOGIC; Clk : in STD_LOGIC); end component IR_Beam_Split; component PWM_to_Digital is Port ( PWM_sig : in STD_LOGIC; Clk : in STD_LOGIC; Digital_out : out STD_LOGIC); end component PWM_to_Digital; component Smooth_Rec is Port ( Sig : in STD_LOGIC; Clk : in STD_LOGIC; Smooth : out STD_LOGIC); end component Smooth_Rec; signal convert_rx_out, convert_rx_in : std_logic; signal cout : std_logic_vector (8 downto 0); begin Ir_out : IR_Beam_Split port map( LED => Leds(0), RX => Rxs(0), Clk => Clk); Ir_in : IR_Beam_Split port map( LED => Leds(1), RX => Rxs(1), Clk => Clk); --turns noisy signal from sensors to digital signal Smooth_out : Smooth_Rec port map( Sig => Rxs(0), Clk => Clk, Smooth => convert_rx_out); Smooth_in : Smooth_Rec port map( Sig => Rxs(1), Clk => Clk, Smooth => convert_rx_in); FS : Full_system port map( O => convert_rx_out, --not Rxs(0) I => convert_rx_in, Clk => Clk, Reset => Reset, Auto => Auto, Set => Set, Light => Light, Count_Output => cout); --debug for seeing if sensors are triggered O_light <= convert_rx_out; I_light <= convert_rx_in; --debug to see if counting people in room properly Count_out <= cout; end Behavioral;