---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:51:34 11/21/2014 -- Design Name: -- Module Name: soundWaveGenerator - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity soundWaveGenerator is Port ( CLK : in STD_LOGIC; PITCH : in STD_LOGIC_VECTOR(9 downto 0); EN : in STD_LOGIC; SOUND : out STD_LOGIC); end soundWaveGenerator; architecture Behavioral of soundWaveGenerator is component clk_div2 is port (clk : in STD_LOGIC; pitch_div : in STD_LOGIC_VECTOR(9 downto 0); sound_div : out STD_LOGIC); end component; signal temp_s : STD_LOGIC; begin CD: clk_div2 port map ( CLK => CLK, pitch_div => PITCH, sound_div => temp_s); MAKE_SOUND: process (EN,CLK, pitch) begin if (EN = '0') then SOUND <= '0'; else SOUND <= temp_s; end if; end process; end Behavioral;