---------------------------------------------------------------------------------- -- Zack Eldredge, zeldredg@calpoly.edu -- Mark Brown, mbrown73@calpoly.edu -- Behavioral 4 bit counter FSM -- 0 to 10 then back to 0 -- -- Create Date: 23:35:30 11/21/2014 -- Design Name: -- Module Name: level_fsm - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity level_fsm is Port ( En : in STD_LOGIC; Reset : in STD_LOGIC; Level : out STD_LOGIC_VECTOR (3 downto 0)); end level_fsm; architecture Behavioral of level_fsm is signal PS : STD_LOGIC_VECTOR (3 downto 0) := "0000"; --Present state signal signal NS : STD_LOGIC_VECTOR (3 downto 0); --Next state signal begin sync_proc : process (En, NS, Reset) begin if (Reset = '1') then PS <= "0000"; -- Value reset to "0000" if reset is high elsif (rising_edge(En)) then PS <= NS; --Present state assigned next state on the rising edge of enable end if; end process sync_proc; comb_proc : process (PS) begin NS <= PS + "0001"; --Next state is assigned present state incremented by "0001" end process comb_proc; Level <= PS; --Present state signal is connected to the level output end Behavioral;