Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version1909853
date_generatedSat Dec 9 21:54:39 2017 os_platformWIN64
product_versionVivado v2017.2 (64-bit) project_id4233891930604e76afdeb579e770ca24
project_iteration51 random_id43b32d72-508b-413b-895e-77c191d44cc3
registration_id43b32d72-508b-413b-895e-77c191d44cc3 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6500U CPU @ 2.50GHz cpu_speed2592 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram12.000 GB total_processors1

vivado_usage
java_command_handlers
addsources=16 autoconnecttarget=24 closedesign=1 editcopy=1
editdelete=4 editpaste=1 editundo=38 launchprogramfpga=65
newproject=1 openhardwaremanager=27 openrecenttarget=2 runbitgen=54
runimplementation=57 runsynthesis=95 settopnode=3 showview=18
simulationrun=1 toggleviewnavigator=6 viewtaskrtlanalysis=1
other_data
guimode=16
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=1 simulator_language=VHDL srcsetcount=6 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 carry4=28 fdce=23 fdpe=1
fdre=101 gnd=6 ibuf=6 ldce=26
lut1=96 lut2=35 lut3=13 lut4=22
lut5=18 lut6=19 obuf=16 vcc=9
pre_unisim_transformation
bufg=1 carry4=28 fdce=23 fdpe=1
fdre=101 gnd=6 ibuf=6 ldce=26
lut1=96 lut2=35 lut3=13 lut4=22
lut5=18 lut6=19 obuf=16 vcc=9

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=28
fdce_functional_category=Flop & Latch fdce_used=23 fdpe_functional_category=Flop & Latch fdpe_used=1
fdre_functional_category=Flop & Latch fdre_used=101 ibuf_functional_category=IO ibuf_used=6
ldce_functional_category=Flop & Latch ldce_used=26 lut1_functional_category=LUT lut1_used=3
lut2_functional_category=LUT lut2_used=35 lut3_functional_category=LUT lut3_used=13
lut4_functional_category=LUT lut4_used=22 lut5_functional_category=LUT lut5_used=18
lut6_functional_category=LUT lut6_used=19 obuf_functional_category=IO obuf_used=16
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=91 lut_as_logic_util_percentage=0.44
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=125 register_as_flip_flop_util_percentage=0.30
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=26 register_as_latch_util_percentage=0.06
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=91 slice_luts_util_percentage=0.44
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=151 slice_registers_util_percentage=0.36
fully_used_lut_ff_pairs_fixed=0.36 fully_used_lut_ff_pairs_used=2 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=91 lut_as_logic_util_percentage=0.44
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=17
lut_ff_pairs_with_one_unused_lut_output_fixed=17 lut_ff_pairs_with_one_unused_lut_output_used=14 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=19 lut_flip_flop_pairs_util_percentage=0.09 slice_available=8150 slice_fixed=0
slice_used=53 slice_util_percentage=0.65 slicel_fixed=0 slicel_used=45
slicem_fixed=0 slicem_used=8 unique_control_sets_used=11 using_o5_and_o6_fixed=11
using_o5_and_o6_used=19 using_o5_output_only_fixed=19 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=72
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=242812 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=11
dsp=0 effort=2 estimated_expansions=173196 ff=151
global_clocks=1 high_fanout_nets=0 iob=22 lut=101
movable_instances=327 nets=424 pins=1834 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=competitive_buzzer_system -verilog_define=default::[not_specified]
usage
elapsed=00:00:31s hls_ip=0 memory_gain=426.207MB memory_peak=650.102MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::