---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 06/03/2018 06:01:54 PM -- Design Name: -- Module Name: concatenate - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity concatenate is Port ( A : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); C : out STD_LOGIC_VECTOR (10 downto 0)); end concatenate; architecture Behavioral of concatenate is begin end Behavioral;