---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/18/2018 02:07:59 PM -- Design Name: -- Module Name: Lab_3 - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity subtractor is Port ( A: in std_logic_vector(7 downto 0); B: in std_logic_vector(7 downto 0); Sum: out std_logic_vector(7 downto 0); Co: out std_logic); end subtractor; architecture Behavioral of subtractor is --component declaration component FullAdder is Port(A, B, Cin: in std_logic; Sum, Co : out std_logic); end component; component HA is Port(OP_A, OP_B: in std_logic; Sum, Co : out std_logic); end component; --intermediate signal declaration signal C0, C1, C2, C3, C4, C5 : std_logic; signal temp : std_logic_vector(7 downto 0); --signal newB : std_logic_vector(7 downto 0); begin --instantiate and port map modules temp <= not B; f0 : FullAdder port map (A => A(0), B => temp(0), Cin => '1', Co => C0, Sum => Sum(0)); f1 : FullAdder port map (A => A(1), B => temp(1), Cin => C0, Co => C1, Sum => Sum(1)); f2 : FullAdder port map (A => A(2), B => temp(2), Cin => C1, Co => C2, Sum => Sum(2)); f3 : FullAdder port map (A => A(3), B => temp(3), Cin => C2, Co => C3, Sum => Sum(3)); f4 : FullAdder port map (A => A(4), B => temp(4), Cin => C3, Co => C4, Sum => Sum(4)); f5 : FullAdder port map (A => A(5), B => temp(5), Cin => C4, Co => C5, Sum => Sum(5)); f6 : FullAdder port map (A => A(6), B => temp(6), Cin => C5, Co => Co, Sum => Sum(6)); end Behavioral;