---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/13/2018 09:51:01 AM -- Design Name: -- Module Name: Final_DFF2 - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Final_DFF2 is Port ( BTN : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC); end Final_DFF2; architecture Behavioral of Final_DFF2 is component DFF is Port ( CLK : in STD_LOGIC; D : in STD_LOGIC; Q : out STD_LOGIC); end component; component clk_div2 is Port ( clk : in std_logic; sclk : out std_logic); end component; signal div2dff : STD_LOGIC; begin CLK0: clk_div2 port map ( clk => CLK, sclk => div2dff); DFF0: DFF port map ( D => BTN, Q => Q, CLK => div2dff); end Behavioral;