-- Mark Williams -- Kenny Doran -- Ash Patel library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SmartFan is Port ( clk : in STD_LOGIC; btns : in STD_LOGIC_VECTOR (4 downto 0); Tinsidei : in STD_LOGIC_VECTOR (6 downto 1); Toutsidei : in STD_LOGIC_VECTOR (6 downto 1); TdesiredIn : in STD_LOGIC_VECTOR (7 downto 0); ToleranceIni : in STD_LOGIC_VECTOR (3 downto 0); seg : out STD_LOGIC_VECTOR (7 downto 0); an : out STD_LOGIC_VECTOR (3 downto 0); fanled : out STD_LOGIC; fan : out STD_LOGIC); end SmartFan; architecture Behavioral of SmartFan is component RCA is PORT( A : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); S : out STD_LOGIC_VECTOR (7 downto 0)); end component RCA; component Multiplexer is PORT( a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); c : in STD_LOGIC_VECTOR (7 downto 0); d : in STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC_VECTOR (4 downto 0); out : out STD_LOGIC_VECTOR (7 downto 0)); end component Multiplexer; component Comparator is PORT( A : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); EQ : out STD_LOGIC; GT : out STD_LOGIC; LT : out STD_LOGIC); end component Comparator; component DFF is PORT( clk : in STD_LOGIC; d : in STD_LOGIC_VECTOR (7 downto 0); en : in STD_LOGIC; f : out STD_LOGIC_VECTOR (7 downto 0)); end component DFF; component sseg_dec is PORT( ALU_VAL : in std_logic_vector(7 downto 0); SIGN : in std_logic; VALID : in std_logic; CLK : in std_logic; DISP_EN : out std_logic_vector(3 downto 0); SEGMENTS : out std_logic_vector(7 downto 0)); end component sseg_dec; signal Tinside, Toutside, ToleranceIn : std_logic_vector(7 downto 0):= x"00"; signal tolerance : std_logic_vector(7 downto 0):= x"02"; signal Tdesired : std_logic_vector(7 downto 0):= x"48"; signal adjin, adjout, binnum : std_logic_vector(7 downto 0); signal lt0, lt1, gt0, gt1, fansig : std_logic; begin Tinside(6) <= Tinsidei(6); Tinside(5) <= Tinsidei(5); Tinside(4) <= Tinsidei(4); Tinside(3) <= Tinsidei(3); Tinside(2) <= Tinsidei(2); Tinside(1) <= Tinsidei(1); Toutside(6) <= Toutsidei(6); Toutside(5) <= Toutsidei(5); Toutside(4) <= Toutsidei(4); Toutside(3) <= Toutsidei(3); Toutside(2) <= Toutsidei(2); Toutside(1) <= Toutsidei(1); ToleranceIn(3) <= ToleranceIni(3); ToleranceIn(2) <= ToleranceIni(2); ToleranceIn(1) <= ToleranceIni(1); ToleranceIn(0) <= ToleranceIni(0); DFF0: DFF Port Map(clk => clk, d=> ToleranceIn, en => btns(0), f=> Tolerance); DFF1: DFF Port Map(clk => clk, d=> TdesiredIn, en => btns(0), f=> Tdesired); RCA0: RCA Port Map(A => tolerance, B => Tinside, S => adjin); RCA1: RCA Port Map(A => tolerance, B => Toutside, S => adjout); C0: Comparator Port Map(A => Tinside, B =>adjout, LT => lt0); C1: Comparator Port Map(A => adjin, B =>Toutside, GT => gt0); C2: Comparator Port Map(A => Tinside, B =>Tdesired, LT => lt1, GT => gt1); M0: Multiplexer Port Map(a => Tinside, b => Tdesired, c => Toutside, d=> Tolerance, sel => btns, out => binnum); Display: sseg_dec Port Map(ALU_VAL => binnum, SIGN => '0', VALID => '1', CLK => clk, DISP_EN => an, SEGMENTS => seg); fansig <= ((lt0 and lt1) or (gt0 and gt1)) and not (gt0 and lt0); Fan <= fansig; fanled <= fansig; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Multiplexer is Port ( a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); c : in STD_LOGIC_VECTOR (7 downto 0); d : in STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC_VECTOR (4 downto 0); out : out STD_LOGIC_VECTOR (7 downto 0)); end Multiplexer; architecture Behavioral of Multiplexer is begin with sel select out <= a when "00010", b when "00100", c when "01000", d when "10000", x"00" when others; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity DFF is Port ( clk : in STD_LOGIC; d : in STD_LOGIC_VECTOR (7 downto 0); en : in STD_LOGIC; f : out STD_LOGIC_VECTOR (7 downto 0)); end DFF; architecture Behavioral of DFF is begin process (clk) is begin if rising_edge(clk) then if (en='1') then f <= d; end if; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Comparator is Port ( A : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); EQ : out STD_LOGIC; GT : out STD_LOGIC; LT : out STD_LOGIC); end Comparator; architecture Behavioral of Comparator is begin EQ <= '1' when (A=B) else '0'; GT <= '1' when (A>B) else '0'; LT <= '1' when (A