---------------------------------------------------------------------------------- -- Company: Cal Poly EE -- Engineer: Victoria Law, Brad Levin, Jessica Patterson, Anna Vojvoda -- Project Name: Final Project Fall 2016-- Company: -- Create Date: 11/17/2016 01:55:04 PM -- Design Name: Counter -- Module Name: counter - Behavioral ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( sw : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC); end counter; architecture Behavioral of counter is signal count: std_logic_vector(1 downto 0); signal done: std_logic; begin process (sw, clk, count, done) begin if (sw = '0') then count <= "00"; done <= '0'; elsif (rising_edge(clk) and sw = '1') then if (count = "00" or count = "01" or count = "10") then count <= (count + 1); done <= '0'; Elsif (count = "11" and sw = '1') then done <= '1'; count <= "00"; End if; End if; End process; Q <= done; End Behavioral;