---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:37:46 12/01/2014 -- Design Name: -- Module Name: Ledcontroller - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Ledcontroller is Port ( s1 : in STD_LOGIC; s2 : in STD_LOGIC; s3: in STD_LOGIC; s4: in STD_LOGIC; s5: in STD_LOGIC; s6: in STD_LOGIC; s7: in STD_LOGIC; s8: in STD_LOGIC; clk : in std_logic; reset : in std_logic; ledson : in std_logic_vector(7 downto 0); updates: out std_logic; leds : out std_logic_vector (7 downto 0) ); end Ledcontroller; architecture Behavioral of Ledcontroller is signal led: std_logic_vector(7 downto 0) := "00000000"; signal update : std_logic_vector(7 downto 0):= "01000000"; signal updatess : std_logic; begin process(updatess) begin updates <= updatess; end process; process(s1,s2,s3,s4,s5,s6,s7,s8,ledson,clk,reset,led,update) begin leds <= led; if (rising_edge (clk)) then if reset = '1' then led <= "00000000"; updatess <= '1'; else if updatess = '1' then led <= ledson; updatess <= '0'; update <= "00000000"; end if; updatess <= '0'; if ((s1 and s2 and s3 and s4 and s5 and s6 and s7 and s8) = '1' and update = "11111111") then updatess <= '1'; led <= ledson; else updatess <= (update(0) and update(1) and update(2) and update(3) and update(4) and update(5) and update(6) and update(7)); if (s1 = '1') then led(0) <= '0'; else if led(0) = '0' then update(0) <= '1'; else led(0) <= ledson(0); update(0) <= '0'; end if; end if; if (s2 = '1') then led(1) <= '0'; else if led(1) = '0' then update(1) <= '1'; else led(1) <= ledson(1); update(0) <= '0'; end if; end if; if s3 = '1' then led(2) <= '0'; else if led(2) = '0' then update(2) <= '1'; else led(2) <= ledson(2); update(2) <= '0'; end if; end if; if s4 = '1' then led(3) <= '0'; else if led(3) = '0' then update(3) <= '1'; else led(3) <= ledson(3); update(3) <= '0'; end if; end if; if s5 = '1' then led(4) <= '0'; else if led(4) = '0' then update(4) <= '1'; else led(4) <= ledson(4); update(4) <= '0'; end if; end if; if s6 = '1' then led(5) <= '0'; else if led(5) = '0' then update(5) <= '1'; else led(5) <= ledson(5); update(5) <= '0'; end if; end if; if s7 = '1' then led(6) <= '0'; else if led(6) = '0' then update(6) <= '1'; else led(6) <= ledson(6); update(6) <= '0'; end if; end if; if s8 = '1' then led(7) <= '0'; else if led(7) = '0' then update(7) <= '1'; else led(7) <= ledson(7); update(7) <= '0'; end if; end if; end if; end if; end if; end process; end Behavioral;