---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:57:33 11/23/2014 -- Design Name: -- Module Name: InputWait - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Check_Input is Port ( --Counter_Max : in STD_LOGIC; BTN : in STD_LOGIC_VECTOR( 3 downto 0 ); LED : in STD_LOGIC_VECTOR( 3 downto 0 ); G_OVER: out STD_LOGIC; Start_State: out STD_LOGIC); end Check_Input; architecture Behavioral of Check_Input is component LEDtoBTN is Port ( LED : in STD_LOGIC_VECTOR (3 downto 0); BTN : out STD_LOGIC_VECTOR (3 downto 0)); end component LEDtoBTN; component Compare is Port ( LED: in STD_LOGIC_VECTOR ( 3 downto 0 ); BTN: in STD_LOGIC_VECTOR ( 3 downto 0 ); G_OVER: out STD_LOGIC; Start_State: out STD_LOGIC); end component Compare; signal LEDBTN_VAL : std_logic_vector( 3 downto 0 ); begin BTN_mapping : LEDtoBTN port map ( LED => LED, BTN => LEDBTN_VAL); Comparison : Compare port map ( LED => LEDBTN_VAL, BTN => BTN, G_OVER => G_OVER, Start_State => Start_State); end Behavioral;