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-- Company: 
-- Engineer: 
-- 
-- Create Date: 11/27/2016 04:59:16 PM
-- Design Name: 
-- Module Name: disp_clk - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity disp_clk is
    Port ( RSLT : in STD_LOGIC_VECTOR (6 downto 0);
           PC : in STD_LOGIC_VECTOR (6 downto 0);
           CC : in STD_LOGIC_VECTOR (6 downto 0);
           AN : in STD_LOGIC_VECTOR (3 downto 0);
           C : out STD_LOGIC_VECTOR (6 downto 0));
end disp_clk;

architecture Behavioral of disp_clk is

begin
    process (AN) is
    begin
        case (AN) is
        when "1110" =>
            C <= RSLT;
        when "1011" =>
            C <= CC;
        when "0111" => 
            C <= PC;
        when others =>
            C <= "1111111";
    end case;
    end process;
end Behavioral;