`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: Ratner Surf Design // Engineer: James Ratner // // Create Date: 09/08/2018 07:17:37 PM // Design Name: // Module Name: reg_nb // Project Name: // Target Devices: // Tool Versions: // Description: Model for generic register (defaults to 8 bits) // with asynchronous clear // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module reg_nb(data_in, clk, clr, data_out); parameter n = 32; input [n-1:0] data_in; input clk, clr; // input integer init; output reg [n-1:0] data_out; integer init = 10000000; always @ (posedge clr, posedge clk) begin if (clr == 1) // Try: get rid of ld input and just use "if clr == 1" and else // Synth Warning: Mix of synchronous and asynchronous control for reg data_out_reg // Synth Warning: basically this is the SR Flip Flop problem where S and R are both 1 (not allowed) // Getting a Synth Warning saying there is an S and R in here with same priority data_out <= init; else if (clr == 0) data_out <= data_in; end endmodule