---------------------------------------------------------------------------------- -- Company: Cal Poly CPE 133 Project -- Engineer: -- -- Create Date: 11/13/2015 06:29:30 PM -- Design Name: -- Module Name: main_circuit - Behavioral -- Project Name: Solar Room Temperature Regulator -- Target Devices: -- Tool Versions: -- Description: This module allows for the a value to be stored as memory for one complete clock cycle of the main_circuit. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Counter is Port ( EN : in STD_LOGIC; -- Will determine whether the present state value should be stored for the next clock cycle. S_CLK : in STD_LOGIC; -- The clock frequency that runs the flip flop. DATA : in STD_LOGIC; -- The present state value. Q : out STD_LOGIC :='0'); -- The next state value stored for memory. end Counter; architecture Behavioral of Counter is begin DFF : process(EN, S_CLK) begin --This process allows for the circuit to store the previous state of a certain if (rising_edge(S_CLK)) then -- of a certain value, and stores it as memory for one whole clock cycle. if (EN = '1') then Q <= DATA; end if; end if; end process DFF; end Behavioral;