---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05/30/2018 02:32:10 PM -- Design Name: -- Module Name: freqToSound - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity freqToSound is Port ( clk : in STD_LOGIC; freq : in integer; output : out STD_LOGIC); end freqToSound; architecture Behavioral of freqToSound is signal count : integer := 0; signal tmp : std_logic := '0'; begin process(clk, freq) begin if rising_edge(clk) then count <= count + 1; if count >= freq then tmp <= not tmp; count <= 0; end if; end if; output <= tmp; end process; end Behavioral;