Altium

Design Rule Verification Report

Date: 10/10/2016
Time: 03:28:14
Elapsed Time: 00:00:00
Filename: C:\Users\Souley\Desktop\PCB_Project\PCB1.PcbDoc
Warnings: 0
Rule Violations: 14

Summary

Warnings Count
Total 0

Rule Violations Count
Room Sheet1 (Bounding Region = (27.051mm, 27.305mm, 133.858mm, 69.469mm) (InComponentClass('Sheet1')) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Net Antennae (Tolerance=0mm) (All) 0
Silk to Silk (Clearance=0.254mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) 12
Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) 1
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Hole Size Constraint (Min=0.025mm) (Max=3.1mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Width Constraint (Min=0.254mm) (Max=0.254mm) (Preferred=0.254mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Clearance Constraint (Gap=0.254mm) (All),(All) 1
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Total 14

Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (0.097mm < 0.254mm) Between Track (119.548mm,63.783mm)(131.348mm,63.783mm) on Top Overlay And Pad J11-16(128.143mm,60.833mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.097mm]
Silk To Solder Mask Clearance Constraint: (0.097mm < 0.254mm) Between Track (119.548mm,34.243mm)(131.348mm,34.243mm) on Top Overlay And Pad J11-15(128.143mm,37.193mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.097mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (92.837mm,49.022mm)(93.066mm,49.022mm) on Top Overlay And Pad R5-2(94.107mm,49.022mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (87.528mm,49.022mm)(87.757mm,49.022mm) on Top Overlay And Pad R5-1(86.487mm,49.022mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (63.652mm,39.878mm)(63.881mm,39.878mm) on Top Overlay And Pad R1-2(62.611mm,39.878mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (68.961mm,39.878mm)(69.19mm,39.878mm) on Top Overlay And Pad R1-1(70.231mm,39.878mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (56.413mm,35.179mm)(56.642mm,35.179mm) on Top Overlay And Pad R2-2(55.372mm,35.179mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (61.722mm,35.179mm)(61.951mm,35.179mm) on Top Overlay And Pad R2-1(62.992mm,35.179mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (42.418mm,49.022mm)(42.418mm,49.251mm) on Top Overlay And Pad R4-2(42.418mm,50.292mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (42.418mm,43.713mm)(42.418mm,43.942mm) on Top Overlay And Pad R4-1(42.418mm,42.672mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (33.401mm,55.245mm)(33.401mm,55.474mm) on Top Overlay And Pad R3-2(33.401mm,56.515mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]
Silk To Solder Mask Clearance Constraint: (0.239mm < 0.254mm) Between Track (33.401mm,49.936mm)(33.401mm,50.165mm) on Top Overlay And Pad R3-1(33.401mm,48.895mm) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.239mm]

Back to top

Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.056mm < 0.254mm) Between Via (105.486mm,41.783mm) from Top Layer to Bottom Layer And Pad U11-11(103.492mm,41.783mm) on Top Layer [Top Solder] Mask Sliver [0.056mm]

Back to top

Clearance Constraint (Gap=0.254mm) (All),(All)
Clearance Constraint: (0.158mm < 0.254mm) Between Track (126.365mm,46.858mm)(127.838mm,45.385mm) on Top Layer And Pad J11-2(128.143mm,46.473mm) on Multi-Layer

Back to top