---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/05/2018 12:54:32 PM -- Design Name: -- Module Name: final_proj_main - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity final_proj_main is Port ( ms : in STD_LOGIC; orx : in STD_LOGIC; ns : in STD_LOGIC; td : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end final_proj_main; architecture Behavioral of final_proj_main is component dff is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC; en : in STD_LOGIC); end component; signal qn : STD_LOGIC_VECTOR (2 downto 0); begin dff0: dff port map( d => qn(0), clk => clk, q => q(0), en => '1'); dff1: dff port map( d => qn(1), clk => clk, q => q(1), en => '1'); dff2: dff port map( d => qn(2), clk => clk, q => q(2), en => '1'); end Behavioral;