library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity COUNT_8B is port( RESET,CLK:in std_logic; UP,DN:in std_logic; COUNT:out std_logic_vector(7 downto 0); SIGN:out std_logic); end entity COUNT_8B; architecture COUNT_8B of COUNT_8B is signal CNT:unsigned(7 downto 0); signal SGN:std_logic; begin process(CLK,RESET) begin if(RESET='1') then CNT<=(others=>'0');SGN<='0'; elsif(rising_edge(CLK)) then if (CNT=0 and Up='0' and DN<='0')then SGN<='0'; elsif(CNT=0 and UP='1') then CNT<=CNT+1; SGN<='0'; elsif (CNT=0 and DN='1') then CNT<=CNT-1; SGN<='1'; elsif(UP='1' and SGN='0') then CNT<=CNT+1; elsif(UP='1' and SGN='1') then CNT<=CNT+1; elsif(DN='1' and SGN='0') then CNT<=CNT-1; elsif(DN='1' and SGN='1') then CNT<=CNT-1; end if; end if; end process; COUNT<=std_logic_vector(CNT); SIGN<=SGN; end COUNT_8B;