`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Lilly Paul & Kyle Brunnett
// 
// Create Date: 12/01/2016 09:31:21 AM
// Design Name: 
// Module Name: tdoa
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tdoa(
    input GATE1,
    input GATE2,
    input clock,
    output logic [31:0] TDOA_VAL,
    output logic GATE1_OUT,
    output logic GATE2_OUT
    );
    
    logic counting = 0;
    logic trig1 = 0;
    logic trig2 = 0;
    logic [31:0] count = 'h00000000;
    logic [31:0] tdoa_temp = 'h00000000;
    
    always @( posedge clock ) begin
        if (GATE1 == 'b1) begin
            trig1 = 'b1;
        end 
        if (GATE2 == 'b1) begin
            trig2 = 'b1;
        end
        if (GATE1 == 'b0 && GATE2 == 'b0) begin
            trig1 = 'b0;
            trig2 = 'b0;
        end
        
        if ((trig1 == 'b1) && (trig2 == 'b1)) begin
            GATE2_OUT = 'b1;
            tdoa_temp = count;
        end
        else if (trig1 == 'b1) begin
            GATE1_OUT = 'b1;
            count = count + 1;
        end
        else if (trig2 == 'b1) begin
            GATE1_OUT = 'b0;
            count = count - 1;
        end
        else begin
            GATE2_OUT = 'b0;
            count = 0;
        end
    end
    
    always_comb begin
        TDOA_VAL <= tdoa_temp;
    end
    
endmodule