module binary_sorter(sw,mux_out); //top level module output[3:0] mux_out; wire[3:0] qa,qb,qc,qd; parameter[3:0] a = 4'b1101, b = 4'b1111, c = 4'b1010 ,d = 4'b0010; input wire[1:0] sw; wire[15:0] dec_a, dec_b,dec_c, dec_d; wire[15:0] or_out; wire[15:0] dec_1,dec_4; wire[15:0] dec_in2,dec_in3; decoder_4_16 decode1(a,dec_a); decoder_4_16 decode2(b,dec_b); decoder_4_16 decode3(c,dec_c); decoder_4_16 decode4(d,dec_d); or_ckt or1(dec_a,dec_b,dec_c,dec_d,or_out); priority_encoder_high enc1(or_out,qa); decoder_4_16 decoder1(qa,dec_1); remove_number num1(dec_1,dec_in2,or_out); priority_encoder_high enc2(dec_in2,qb); priority_encoder_low enc4(or_out,qd); decoder_4_16 decoder4(qd,dec_4); remove_number num2(dec_4,dec_in3,or_out); priority_encoder_low enc3(dec_in3,qc); select_one choose(sw,qa,qb,qc,qd,mux_out) ; endmodule module decoder_4_16(in,out); // decoder module input[3:0] in; output[15:0] out; reg[15:0] out; always@* begin out= 0; case(in) 4'h0: out= 16'h0001; 4'h1: out= 16'h0002; 4'h2: out= 16'h0004; 4'h3: out= 16'h0008; 4'h4: out= 16'h0010; 4'h5: out= 16'h0020; 4'h6: out= 16'h0040; 4'h7: out= 16'h0080; 4'h8: out= 16'h0100; 4'h9: out= 16'h0200; 4'hA: out= 16'h0400; 4'hB: out= 16'h0800; 4'hC: out= 16'h1000; 4'hD: out= 16'h2000; 4'hE: out= 16'h4000; 4'hF: out= 16'h8000; endcase end endmodule //priority encoder high to low module priority_encoder_high(in, binary_out); input[15:0] in; output[3:0] binary_out; reg[3:0] binary_out; always@* begin binary_out= 0; if (in[15]) binary_out=4'hF; else if (in[14]) binary_out=4'hE else if (in[13]) binary_out=4'hD; else if (in[12]) binary_out=4'hC; else if (in[11]) binary_out=4'hB; else if (in[10]) binary_out=4'hA; else if (in[9]) binary_out=4'h9; else if (in[8]) binary_out=4'h8; else if (in[7]) binary_out=4'h7; else if (in[6]) binary_out=4'h6; else if (in[5]) binary_out=4'h5; else if (in[4]) binary_out=4'h4; else if (in[3]) binary_out=4'h3; else if (in[2]) binary_out=4'h2; else if (in[1]) binary_out=4'h1; else if (in[0]) binary_out=4'h0; end endmodule //priority encoder low to high module priority_encoder_low(in, binary_out); input[15:0] in; output[3:0] binary_out; reg[3:0] binary_out; always@* begin binary_out= 0; if (in[0]) binary_out=4'h0; else if (in[1]) binary_out=4'h1; else if (in[2]) binary_out=4'h2; else if (in[3]) binary_out=4'h3; else if (in[4]) binary_out=4'h4; else if (in[5]) binary_out=4'h5; else if (in[6]) binary_out=4'h6; else if (in[7]) binary_out=4'h7; else if (in[8]) binary_out=4'h8; else if (in[9]) binary_out=4'h9; else if (in[10]) binary_out=4'hA; else if (in[11]) binary_out=4'hB; else if (in[12]) binary_out=4'hC; else if (in[13]) binary_out=4'hD; else if (in[14]) binary_out=4'hE; else if (in[15]) binary_out=4'hF; end endmodule //next priority generator module remove_number(dec_out,dec_in,or_out); input wire[15:0] dec_out, or_out; output wire[15:0] dec_in; assign dec_in= (or_out&(~(dec_out))) ; endmodule //or-er circuit to OR all ith bits of all decoders module or_ckt(dec_in1,dec_in2,dec_in3,dec_in4, or_out); input[15:0] dec_in1,dec_in2,dec_in3,dec_in4; output[15:0] or_out; assign or_out[15]= (dec_in1[15]||dec_in2[15]||dec_in3[15]||dec_in4[15]); assign or_out[14]= (dec_in1[14]||dec_in2[14]||dec_in3[14]||dec_in4[14]); assign or_out[13]= (dec_in1[13]||dec_in2[13]||dec_in3[13]||dec_in4[13]); assign or_out[12]= (dec_in1[12]||dec_in2[12]||dec_in3[12]||dec_in4[12]); assign or_out[11]= (dec_in1[11]||dec_in2[11]||dec_in3[11]||dec_in4[11]); assign or_out[10]= (dec_in1[10]||dec_in2[10]||dec_in3[10]||dec_in4[10]); assign or_out[9]= (dec_in1[9]||dec_in2[9]||dec_in3[9]||dec_in4[9]); assign or_out[8]= (dec_in1[8]||dec_in2[8]||dec_in3[8]||dec_in4[8]); assign or_out[7]= (dec_in1[7]||dec_in2[7]||dec_in3[7]||dec_in4[7]); assign or_out[6]= (dec_in1[6]||dec_in2[6]||dec_in3[6]||dec_in4[6]); assign or_out[5]= (dec_in1[5]||dec_in2[5]||dec_in3[5]||dec_in4[5]); assign or_out[4]= (dec_in1[4]||dec_in2[4]||dec_in3[4]||dec_in4[4]); assign or_out[3]= (dec_in1[3]||dec_in2[3]||dec_in3[3]||dec_in4[3]); assign or_out[2]= (dec_in1[2]||dec_in2[2]||dec_in3[2]||dec_in4[2]); assign or_out[1]= (dec_in1[1]||dec_in2[1]||dec_in3[1]||dec_in4[1]); assign or_out[0]= (dec_in1[0]||dec_in2[0]||dec_in3[0]||dec_in4[0]); endmodule //mux module module select_one(sw,qa,qb,qc,qd,mux_out); input wire[1:0] sw; //select lines input wire[3:0] qa,qb,qc,qd; // 4 bit input output[3:0] mux_out; // mux output reg[3:0] mux_out; always@* begin mux_out=0; case(sw) 2'b00: mux_out= qa ; 2'b01: mux_out= qb ; 2'b10: mux_out= qc ; 2'b11: mux_out= qd ; endcase end endmodule