---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11/21/2016 09:54:18 AM -- Design Name: -- Module Name: Timer - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.numeric_std.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Timer is Port (Start : in std_logic; Reset : in std_logic; Clk : in std_logic; T_out : out std_logic); end Timer; architecture Behavioral of Timer is constant max_c : integer := 100000000; begin Time_Alert : process(Start, Reset, Clk) variable count : integer := 0; begin if(rising_edge(Clk)) then T_out <= '0'; if(count = max_c - 1) then T_out <= '1'; count := count + 1; elsif(count = max_c) then T_out <= '1'; count := 0; elsif(count = 0 AND start = '1') then count := 1; elsif(count /= 0 AND Reset = '1') then count := 0; T_out <= '0'; elsif count /= 0 then count := count + 1; end if; end if; end process; end Behavioral;