---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/06/2018 01:48:51 PM -- Design Name: -- Module Name: Main_file - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Main_file is Port ( CLK, RESET, UP: in STD_LOGIC; DIN : in std_logic_vector (13 downto 0); DISP_EN : out std_logic_vector(3 downto 0); light: out STD_LOGIC; light_sensor: in STD_LOGIC; SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0)); end Main_file; architecture Behavioral of Main_file is component clk_div2 is Port ( clk: in std_logic; sclk: out std_logic); end component; component seven_bit_counter is Port ( RESET, CLK, LD, UP : in STD_LOGIC; DIN : in STD_LOGIC_VECTOR (13 downto 0); COUNT : out STD_LOGIC_VECTOR (13 downto 0)); end component; component sseg_dec_uni is Port ( COUNT1 : in std_logic_vector(13 downto 0); COUNT2 : in std_logic_vector(7 downto 0); SEL : in std_logic_vector(1 downto 0); dp_oe : in std_logic; dp : in std_logic_vector(1 downto 0); CLK : in std_logic; SIGN : in std_logic; VALID : in std_logic; DISP_EN : out std_logic_vector(3 downto 0); SEGMENTS : out std_logic_vector(7 downto 0)); end component; signal start_o: std_logic; signal cout: std_logic_vector (13 downto 0); begin turn: process(cout,light_sensor) begin if (light_sensor ='1') then light <= '1'; if(cout = "00000000000000" ) then light <= '0'; end if; elsif (light_sensor ='0') then light <= '0'; end if; end process; start1: clk_div2 port map( clk=> CLK, sclk => start_o); part2: seven_bit_counter port map( RESET => RESET, CLK => start_o, LD => light_sensor, UP => UP, DIN => DIN, COUNT=> cout); display: sseg_dec_uni port map( COUNT1 => cout, COUNT2 => "00000000", SEL => "10", dp_oe => '0', dp => "00", CLK => CLK, SIGN => '0', VALID => '1', DISP_EN => DISP_EN, SEGMENTS => SEGMENTS); end Behavioral;