---------------------------------------------------------------------------------- -- Company: Cal Poly CPE 133 Project -- Engineer: -- -- Create Date: 11/13/2015 06:29:30 PM -- Design Name: -- Module Name: main_circuit - Behavioral -- Project Name: Solar Room Temperature Regulator -- Target Devices: -- Tool Versions: -- Description: This module connects structurally with all the other modules created to -- make the whole system work as one unit. -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity main_circuit is Port ( M_CLK : in STD_LOGIC; --Main clock frequncy of the whole system. Enable_CKT: in STD_LOGIC; --Will enable or disable the whole system. switch : in STD_LOGIC_VECTOR (7 downto 0); --Allows for the prest values to changed to a distinguished number, and one switch to view the inside temp. button : in STD_LOGIC_VECTOR (3 downto 0); --Increments the preset value up or down by 1 or 5. vauxp15 : in STD_LOGIC; --Light sensor value put into the system. T_in : in STD_LOGIC; --Inside temparture sensor data. T_out: in STD_LOGIC; --Outside temperature sensor data. LED : inout STD_LOGIC_VECTOR (15 downto 0); --Lights up a certain amount of LEDs due to the light sensor sensitivity. clkget_in : out STD_LOGIC; --The clock that is mapped to the port for the inside temperature probe. clkget_out : out STD_LOGIC; --The clock that is mapped to the port for the outside temperature probe. GETS_in: out STD_LOGIC; --The chip select signal for the inside temp probe. GETS_out: out STD_LOGIC; --The chip select signal for the outside temp probe. display : out STD_LOGIC_VECTOR (7 downto 0); --Decimal number that is displayed on the BASYS board. anode : out STD_LOGIC_VECTOR (3 downto 0); --Determines which part of the display (4 parts) will be enabled or disabled. motor_out : out STD_LOGIC_VECTOR (3 downto 0)); --Drivers to the motor connected to the board. end main_circuit; architecture Behavioral of main_circuit is component XADCdemo is --This component came from the Xilinx website in order to control the light sensor Port ( CLK100MHZ : in STD_LOGIC; -- we have implemented in the system. vauxp6 : in STD_LOGIC; vauxn6 : in STD_LOGIC; vauxp7 : in STD_LOGIC; vauxn7 : in STD_LOGIC; vauxp15 : in STD_LOGIC; vauxn15 : in STD_LOGIC; vauxp14 : in STD_LOGIC; vauxn14 : in STD_LOGIC; sw : in STD_LOGIC_VECTOR (1 downto 0); LED : inout STD_LOGIC_VECTOR (15 downto 0); an : out STD_LOGIC_VECTOR (3 downto 0); dp : out STD_LOGIC; seg : out STD_LOGIC_VECTOR (6 downto 0)); end component XADCdemo; component Compare is --This component is the comparator that compares two values and outputs whether Port ( A : in STD_LOGIC_VECTOR (7 downto 0); -- one value is less than or equal to the other. B : in STD_LOGIC_VECTOR (7 downto 0); LEQ : out STD_LOGIC; G : out STD_LOGIC); end component Compare; component Eight_Bit_Counter is --This component counts an eight bit preset temperature either up or down Port ( S_CLK1 : in STD_LOGIC; -- depending on the button pressed or switch activated. Temperature_In : in STD_LOGIC_VECTOR (7 downto 0); --Credit given to: Xilinx EN1 : in STD_LOGIC; EN2 : in STD_LOGIC; EN3 : in STD_LOGIC; EN4 : in STD_LOGIC; SW5 : in STD_LOGIC; SW10 : in STD_LOGIC; SW15 : in STD_LOGIC; SW20 : in STD_LOGIC; SW25 : in STD_LOGIC; SW30 : in STD_LOGIC; SW35 : in STD_LOGIC; SW_IN : in STD_LOGIC; tempset : out STD_LOGIC_VECTOR (7 downto 0); AN : out STD_LOGIC_VECTOR (3 downto 0); DISP : out STD_LOGIC_VECTOR (7 downto 0)); end component Four_Bit_Counter; component sseg_dec is --This component allows for the eight bit value generated by either the counter or temperature probes Port ( ALU_VAL : in STD_LOGIC_VECTOR (7 downto 0); -- to be displayed as a decimal number on the BASYS 3 board display. This component is not used SIGN : in STD_LOGIC; -- in the main_circuit file, but is used in the Eight_Bit_Counter. We just included it to VALID : in STD_LOGIC; -- not forget about it; it is not necessary to have in in this particular module. CLK : in STD_LOGIC; -- Credit given to: Bryan Mealy - Free Range VHDL -- Cal Poly University DISP_EN : out STD_LOGIC_VECTOR (3 downto 0); -- CPE Professor SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0)); end component sseg_dec; component Motor is --This component controls the stepper motor to either open or close the shutter/curtain. Port ( mot_clk : in STD_LOGIC; --Credit given to: Arduino sw_dir : in STD_LOGIC; -- Simon Monk (Adafruit Website) sw_enable : in STD_LOGIC; sw_speed : in STD_LOGIC; phase_a : out STD_LOGIC; phase_b : out STD_LOGIC; phase_c : out STD_LOGIC; phase_d : out STD_LOGIC); end component Motor; component DFFmot is --This D Flip Flop will obtain and hold the previous input for one whole clock cycle. Port ( D : in STD_LOGIC; F_CLK : in STD_LOGIC; Q : out STD_LOGIC); end component DFFmot; component Motor_Counter is --This Counter component will determine how long the motor will rotate for when the direction is switched. Port ( Enable : in STD_LOGIC; Counter_CLK : in STD_LOGIC; Light : in STD_LOGIC; Move : out STD_LOGIC); end component Motor_Counter; component Temp_inside is --This component is used for both the inside and outside temperature probes Port ( tclk : in STD_LOGIC; -- to obtain a reading from the actual sensor. CS : in STD_LOGIC := '1'; SO : in STD_LOGIC; Temp : out STD_LOGIC_VECTOR(7 downto 0)); end component Temp_inside; component clk_div3 is --This component takes in the main clock signal (or any other clock signal) to slow it down. Port ( div_clk : in STD_LOGIC; --Credit given to: Bryan Mealy -- Cal Poly University sclk : out STD_LOGIC); -- CPE Professor end component clk_div3; component clk_div22 is --This component takes in the main clock signal (or any other clock signal) Port ( clk : in STD_LOGIC; -- to slow it at a different slower frequency than that of clk_div3. --Credit given to: Bryan Mealy - Free Range VHDL sclk : out STD_LOGIC); -- Cal Poly University end component clk_div22; -- CPE Professor --All of the signals below are used to transfer data from one module to another. signal lessoreq1 : STD_LOGIC; --signal to that determines whether temp inside is less than or equal to the temp outside. signal lessoreq2 : STD_LOGIC; --signal to that determines whether user setting temp is less than or equal to the temp inside. signal notlereq1 : STD_LOGIC; --signal to that determines whether temp inside is greater than the temp outside. signal notlereq2 : STD_LOGIC; --signal to that determines whether user setting temp is greater than the temp inside. signal temp_set : STD_LOGIC_VECTOR (7 downto 0); --users temp setting from the eight bit counter. signal motdir : STD_LOGIC; --signal determines whether the motor will open or close the curtain. signal old_motdir : STD_LOGIC; --signal that stores the previous direction of the motor in a D Flip Flop. signal moving : STD_LOGIC; --signal that determines whether the motor will continue to move or stop after a certain amount of time. signal count: STD_LOGIC; --signal that enables the motor counter to start counting. signal clkget : STD_LOGIC; --signal that carries the clock for the temperature probes. signal temp_in : STD_LOGIC_VECTOR (7 downto 0); --signal of the actual reading from the inside temp probe. signal temp_out : STD_LOGIC_VECTOR (7 downto 0); --signal of the actual reading from the outside temp probe. signal GET_in : STD_LOGIC := '1'; --signal that carry the chip select signal that's governed by the GETCLK for inside probe. signal GET_out : STD_LOGIC := '1'; --signal that carry the chip select signal that's governed by the GETCLK for outside probe. signal GETCLK : STD_LOGIC; --signal that is the clock frequency that runs the chip select signal. signal motor_works : STD_LOGIC; -- signal that checks whether the Enable_CKT input is on or off, and will turn the motor on or off accordingly. begin clkdiv3 : clk_div3 port map(div_clk => M_CLK, sclk => clkget); --Will make the main clock frequency 25 times slower. clkdiv4 : clk_div22 port map(clk => M_CLK, sclk => GETCLK); --Will make the main clock frequency 100,000,000 times slower. tempin : Temp_inside port map(tclk => clkget, CS => GET_in, SO => T_in, Temp => temp_in); --Obtains the temperature value of the inside of the room. tempout : Temp_inside port map(tclk => clkget, CS => GET_out, SO => T_out, Temp => temp_out); --Obtains the temperature value of the outside of the room. counter_disp : Eight_Bit_Counter port map(S_CLK1 => M_CLK, Temperature_In => temp_in, EN1 => button(3), EN2 => button(2), EN3 => button(1), EN4 => button(0), SW5 => switch(7), SW10 => switch(6), SW15 => switch(5), SW20 => switch(4), SW25 => switch(3), SW30 => switch(2), SW35 => switch(1), SW_IN => switch(0), tempset => temp_set, AN => anode, DISP => display); -- This connects the inputs of the main_circuit to the eight bit counter and will output the value that will display of the board. comparetito : compare port map(A => temp_in, B => temp_out, LEQ => lessoreq1, G => notlereq1); --This comparator determines whether the temperature inside is less -- than or equal to the temperature of the outside. comparetsti : compare port map(A => temp_set, B => temp_in, LEQ => lessoreq2, G => notlereq2); --This comparator determines whether the preset temperature is less -- than or equal to the temperature of the inside. motdir <= lessoreq1 XOR lessoreq2; --Will find out whether the motor will open or close the curtain in accordance to the outputs of the comparators. flipflop : DFFmot port map(D => motdir, F_CLK => M_CLK, Q => old_motdir); --Will store the previous value of motdir. count <= motdir XOR old_motdir; --Will determine whether the direction of the motor has changed, then it will be enabled. motor_works <= Enable_CKT AND count; --If the whole system is enabled, the the motor will turn. counter_mot : Motor_Counter port map(Enable => motor_works, Counter_CLK => M_CLK, Move => moving, Light => LED(7)); --Will enable the motor to work in a certain direction for a certain amount of time. motorun : Motor port map(mot_clk => M_CLK, sw_dir => motdir, sw_enable => moving, sw_speed => '0', phase_a => motor_out(3), phase_b => motor_out(2), phase_c => motor_out(1), phase_d => motor_out(0)); --This will officially output the motor to run until the motor counter output (moving) goes to '0' to turn the motor off. clkget_out <= clkget; --What we assign the signal of the outside temperature probe clock for the main circuit output. clkget_in <= clkget; --What we assign the signal of the inside temperature probe clock for the main circuit output. lightsensor : XADCdemo port map(clk100mhz => M_CLK, LED => LED, vauxp15 => vauxp15, vauxp6 => '0', vauxn6 => '0', vauxp7 => '0', vauxn7 => '0', vauxn15 => '0', vauxp14 => '0', vauxn14 => '0', sw => "00"); --The port map for the light sensor, which has all ports set to '0' except for the clock, LEDs, and the input of the board (vauxp15) getcycle : process (GET_in, GET_out, GETCLK) --This process allows the chip select (GET_in, GET_out) to alternate regularly. begin if (rising_edge(GETCLK)) then if (GET_in = '1') then GET_in <= '0'; GET_out <= '0'; else GET_in <= '1'; GET_out <= '1'; end if; end if; end process getcycle; get1 : process (GET_in, GET_out, clkget) begin --This process syncs up the chip select signal change to the temp probe clock. if (falling_edge(clkget)) then GETS_in <= GET_in; GETS_out <= GET_out; end if; end process get1; end Behavioral; --Ends the architecture.