--Takes in a 15 bit binary value and spilts it up to 4 digits on a 7 seg display. This comments out code used to enable the fourth digit of the 7 seg display for our purposes on this project --@author Sam Malicoat, Ryan Kendall library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Seg7 is Port ( Input : in STD_LOGIC_VECTOR (11 downto 0); CLK: in STD_LOGIC; Display : out STD_LOGIC_VECTOR (6 downto 0); Enable : out STD_LOGIC_VECTOR (3 downto 0)); end Seg7; architecture Behavioral of Seg7 is component singleDisplay Port ( INPUT : in STD_LOGIC_VECTOR (3 downto 0); Display : out STD_LOGIC_VECTOR (6 downto 0)); end component; Signal D1,D2,D3,D4:STD_LOGIC_VECTOR (6 downto 0):="0000000"; Signal sE: STD_LOGIC_VECTOR (3 downto 0):="0001"; begin Seg1: singleDisplay port map( Input=>Input(3 downto 0), Display=>D1(6 downto 0)); Seg2: singleDisplay port map( Input=>Input(7 downto 4), Display=>D2(6 downto 0)); Seg3: singleDisplay port map( Input=>Input(11 downto 8), Display=>D3(6 downto 0)); process (CLK, sE) is variable count: integer:=0; begin if(rising_edge(CLK))then count := count +1; -- if(count = 1) then if(count = 120000) then count :=0; case (sE) is when "1110"=>sE<="1101"; when "1101"=>sE<="1011"; when others =>sE<="1110"; -- when others=>sE<="1110"; --we only want 3 digits diplayed so we dont want to enable the forth digit for thisproject end case; end if; end if; Enable<=sE; end process; process (D1,D2,D3,D4,sE) is begin case (sE) is when "1110"=>Display<=D1; when "1101"=>Display<=D2; when "1011"=>Display<=D3; when others=>Display<=D4; end case; end process; end Behavioral;