---------------------------------------------------------------------------------- -- Company: Cal Poly San Luis Obispo -- Engineer: Chase Timmins / Shivani Ganti -- -- Create Date: 11/29/2017 11:55:43 AM -- Design Name: -- Module Name: Timer_Div - Behavioral -- Project Name: Pong_Game -- Description: -- -- -- Revision: -- Revision 0.01 - File Created -- Revision 0.02 Removed Div output -- Revision 0.03 Added CEN signal -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Timer_Div is Port ( Clk : in STD_LOGIC; PS : in STD_LOGIC_VECTOR (2 downto 0); Timer : out STD_LOGIC; Clk_out : out STD_LOGIC); end Timer_Div; architecture Behavioral of Timer_Div is -- COMPONENTS component Clk_Div is Port ( Clk : in STD_LOGIC; CEN : in STD_LOGIC; Div : in STD_LOGIC_VECTOR (27 downto 0); Clk_Out : out STD_LOGIC); end component; -- Signals signal Cout, Clk_1s, CEN : std_logic := '0'; signal Div : std_logic_vector (27 downto 0) := X"0000000"; begin -- Initializing Component game_clk: Clk_Div port map (Clk => Clk, CEN => CEN, Div => Div, Clk_Out => Cout); sec_clk: Clk_Div port map (Clk => Clk, CEN => CEN, Div => X"2FAF080", Clk_Out => Clk_1s); -- Outputting Cout to Clk_out Clk_out <= Cout; state: process (PS) begin case (PS) is when "001" => CEN <= '1'; Div <= X"04C4B40"; when "010" => CEN <= '1'; Div <= X"02625A0"; when "011" => CEN <= '1'; Div <= X"0196E6B"; when "100" => CEN <= '1'; Div <= X"01312D0"; when "101" => CEN <= '1'; Div <= X"00F4240"; when others => -- The Start or Game Over State CEN <= '0'; Div <= X"04C4B40"; end case; end process; -- Timing: Uses the Clk_1s to determine the timing output timing: process (Clk_1s) variable count : unsigned (3 downto 0) := X"0"; variable T_Clk : std_logic := '1'; begin if (rising_edge(Clk_1s)) then if (CEN = '1') then count := count + 1; if (count = X"A") then count := X"0"; T_Clk := not T_Clk; elsif (count = X"5") then T_Clk := not T_Clk; end if; end if; Timer <= T_Clk; end if; end process; end Behavioral;