Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
date_generatedSun Jun 08 20:46:30 2014 product_versionVivado v2014.1 (64-bit)
build_version881834 os_platformWIN64
registration_id209858285_209874025_0_811 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a100t
target_packagecsg324 target_speed-3
random_id0cc71d5082ce5287892bd3a171a0cb45 project_id00acfcdc3a33418b8baf0efe1712c3bb
project_iteration1

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-3687U CPU @ 2.10GHz cpu_speed2594 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=2 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1
other_data
guimode=1

unisim_transformation
pre_unisim_transformation
ibuf=4 lut4=1 obuf=1
post_unisim_transformation
ibuf=4 lut4=1 obuf=1

placer
usage
lut=1 ff=0 bram36=0 bram18=0
ctrls=0 dsp=0 iob=5 bufg=0
global_clocks=0 pll=0 bufr=0 nets=10
movable_instances=6 pins=15 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=1.003000

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a100tcsg324-3 package=csg324 speedgrade=-3 version=2014.1
platform=nt64 temp_grade=extended process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=1.000000 pct_inputs_defined=0 user_junc_temp=27.0 (C)
ambient_temp=25.0 (C) user_effective_thetaja=4.562757 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=5.7 (C/W)
user_board_temp=25.0 (C) junction_temp=27.0 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 on-chip_power=0.429057 dynamic=0.330927
effective_thetaja=4.6 thetasa=4.6 (C/W) thetajb=5.7 (C/W) off-chip_power=0.000000
logic=0.002129 signals=0.011254 i/o=0.317545 devstatic=0.098130
vccint_voltage=1.000000 vccint_total_current=0.045265 vccint_dynamic_current=0.029383 vccint_static_current=0.015883
vccaux_voltage=1.800000 vccaux_total_current=0.029265 vccaux_dynamic_current=0.011050 vccaux_static_current=0.018215
vcco33_voltage=3.300000 vcco33_total_current=0.089350 vcco33_dynamic_current=0.085350 vcco33_static_current=0.004000
vcco25_voltage=2.500000 vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco18_voltage=1.800000 vcco18_total_current=0.000000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco15_voltage=1.500000 vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco135_voltage=1.350000 vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco12_voltage=1.200000 vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vccaux_io_voltage=0.000000 vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccbram_voltage=1.000000 vccbram_total_current=0.000261 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000261
mgtavcc_voltage=1.000000 mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavtt_voltage=1.200000 mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
vccadc_voltage=1.800000 vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000
confidence_level_design_state=High confidence_level_clock_activity=Low confidence_level_io_activity=Low confidence_level_internal_activity=Medium
confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=1 slice_luts_loced=0 slice_luts_available=63400 slice_luts_util_percentage=<0.01
lut_as_logic_used=1 lut_as_logic_loced=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=<0.01
lut_as_memory_used=0 lut_as_memory_loced=0 lut_as_memory_available=19000 lut_as_memory_util_percentage=0.00
slice_registers_used=0 slice_registers_loced=0 slice_registers_available=126800 slice_registers_util_percentage=0.00
register_as_flip_flop_used=0 register_as_flip_flop_loced=0 register_as_flip_flop_available=126800 register_as_flip_flop_util_percentage=0.00
register_as_latch_used=0 register_as_latch_loced=0 register_as_latch_available=126800 register_as_latch_util_percentage=0.00
f7_muxes_used=0 f7_muxes_loced=0 f7_muxes_available=31700 f7_muxes_util_percentage=0.00
f8_muxes_used=0 f8_muxes_loced=0 f8_muxes_available=15850 f8_muxes_util_percentage=0.00
slice_used=1 slice_loced=0 slice_available=15850 slice_util_percentage=<0.01
slicel_used=1 slicel_loced=0 slicem_used=0 slicem_loced=0
lut_as_logic_used=1 lut_as_logic_loced=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=<0.01
using_o5_output_only_used=0 using_o5_output_only_loced= using_o6_output_only_used=1 using_o6_output_only_loced=
using_o5_and_o6_used=0 using_o5_and_o6_loced= lut_as_memory_used=0 lut_as_memory_loced=0
lut_as_memory_available=19000 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_loced=0
lut_as_shift_register_used=0 lut_as_shift_register_loced=0 lut_flip_flop_pairs_used=1 lut_flip_flop_pairs_loced=0
lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_util_percentage=<0.01 fully_used_lut_ff_pairs_used=0 fully_used_lut_ff_pairs_loced=
lut_ff_pairs_with_unused_lut_used=0 lut_ff_pairs_with_unused_lut_loced= lut_ff_pairs_with_unused_flip_flop_used=1 lut_ff_pairs_with_unused_flip_flop_loced=
unique_control_sets_used=0 minimum_number_of_registers_lost_to_control_set_restriction_used=0(Lost)
memory
block_ram_tile_used=0 block_ram_tile_loced=0 block_ram_tile_available=135 block_ram_tile_util_percentage=0.00
ramb36_fifo*_used=0 ramb36_fifo*_loced=0 ramb36_fifo*_available=135 ramb36_fifo*_util_percentage=0.00
ramb18_used=0 ramb18_loced=0 ramb18_available=270 ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_loced=0 dsps_available=240 dsps_util_percentage=0.00
clocking
bufgctrl_used=0 bufgctrl_loced=0 bufgctrl_available=32 bufgctrl_util_percentage=0.00
bufio_used=0 bufio_loced=0 bufio_available=24 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_loced=0 mmcme2_adv_available=6 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_loced=0 plle2_adv_available=6 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_loced=0 bufmrce_available=12 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_loced=0 bufhce_available=96 bufhce_util_percentage=0.00
bufr_used=0 bufr_loced=0 bufr_available=24 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_loced=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_loced=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_loced=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_loced=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_loced=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_loced=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_loced=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_loced=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_loced=0 xadc_available=1 xadc_util_percentage=0.00
primitives
ibuf_used=4 ibuf_functional_category=IO obuf_used=1 obuf_functional_category=IO
lut4_used=1 lut4_functional_category=LUT
io_standard
pci33_3=0 lvcmos12=0 sstl135=0 lvttl=0
diff_sstl18_ii=0 hstl_i=0 mobile_ddr=0 hsul_12=0
lvcmos25=0 sstl135_r=0 lvcmos33=1 diff_sstl15=0
hstl_ii=0 lvcmos18=0 lvcmos15=0 hstl_i_18=0
diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0 sstl18_ii=0
sstl15=0 sstl15_r=0 lvds_25=0 diff_hstl_i=0
rsds_25=0 diff_hstl_ii=0 tmds_33=0 diff_hstl_i_18=0
mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0 diff_sstl18_i=0
diff_sstl15_r=0 diff_sstl135=0 diff_sstl135_r=0 diff_mobile_ddr=0
blvds_25=0

router
usage
lut=1 ff=0 bram36=0 bram18=0
ctrls=0 dsp=0 iob=5 bufg=0
global_clocks=0 pll=0 bufr=0 nets=10
movable_instances=6 pins=15 bogomips=0 high_fanout_nets=0
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
estimated_expansions=6630 actual_expansions=704 router_runtime=33.736000

synthesis
command_line_options
-part=xc7a100tcsg324-3 -name=default::[not_specified] -top=circuit1_top -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::4
usage
elapsed=00:00:54s memory_peak=555.164MB memory_gain=379.730MB